With development of the semiconductor industry, requirements for integration and miniaturization of semiconductor chips are increasingly high. To meet the integration and miniaturization requirements for semiconductor chips, package techniques are also continuously improved. Various types of stacked package techniques have also been successively developed and become increasingly important.
Common package techniques include wire bonding (Wire bonding) package, flip-chip bonding (Flip-chip bonding) package, and those derived therefrom including package on package (Package On Package), through silicon via (Through Silicon Via, TSV) package, fan out wafer level package (Fan Out Wafer Level Package, FOWLP), and the like.
In a conventional fan out wafer level package, interconnection of a top chip and a bottom chip is implemented in a stacking direction by providing a channel at a periphery of a package body of the bottom chip, fanning out input/output traces of a die on the bottom chip, in all directions, to a via at the periphery, and filling an electrically conductive material in the via.
In the prior art, there may be one, two, three, or more dies packaged in the bottom chip. The via is provided at the periphery of the package body of the bottom chip. The input/output traces of the die that are required to be connected to the top chip are fanned out in all directions to the via at the periphery of the package body, and go through the via and electrically connects to the top chip.
Therefore, when there are two or more dies in the bottom chip, input/output traces of one die that are required to be connected to the top chip (especially when the die has a large quantity of input/output traces) occupy most of routing space resources at a routing layer and affect traces interconnected dies in the bottom chip and other traces at the routing layer, which consequently causes difficulty of routing or increases a quantity of layers of the routing layer.